Re: [math-fun] XCT instruction
Problems with XCT (execute one instruction): * no clean/obvious semantics; semantics have to be worked out for each different instruction being "executed" * only one level of execute (at least for IBM) * originally used for *tables* of instructions, but what about variable-length instructions? (Similar problem to "skip" instructions) * what are the semantics in the case of interrupts? We now have architectures which support "virtual machines"; analogous problems at much larger scale. At 04:47 PM 3/15/2018, rcs@xmission.com wrote:
PS: Does anyone else miss the XCT instruction? The 7094 & PDP6/10 had it, but it seems to have vanished. I guess it's an architectural nightmare for the hardware folks. --Rich
The GE 645 also had an execute double instruction, which would execute pairs of instructions. I think there were severe constraints on the even/odd-ness of the source, and on the overlaps (none allowed) between segments. Truly a nightmare for hardware. Not sure it ever really worked.
On Mar 15, 2018, at 8:13 PM, Henry Baker <hbaker1@pipeline.com> wrote:
Problems with XCT (execute one instruction):
* no clean/obvious semantics; semantics have to be worked out for each different instruction being "executed"
* only one level of execute (at least for IBM)
* originally used for *tables* of instructions, but what about variable-length instructions? (Similar problem to "skip" instructions)
* what are the semantics in the case of interrupts?
We now have architectures which support "virtual machines"; analogous problems at much larger scale.
At 04:47 PM 3/15/2018, rcs@xmission.com wrote:
PS: Does anyone else miss the XCT instruction? The 7094 & PDP6/10 had it, but it seems to have vanished. I guess it's an architectural nightmare for the hardware folks. --Rich
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The biggest gain from these *tables* of instructions is "dispatching" -- the ability to quickly do a conditional without having to check each case separately in a linear search. Thus, the C language "case" statement allows "dispatching" on all 8-bits of a character in "one instruction". In Fortran this is called "computed GO(TO)". McCarthy's original Lisp had no dispatching abilities, which may have contributed to Lisp's reputation for slowness. Curiously, regular expressions don't have a way to say this sort of thing -- probably because dispatching is a speedup, and doesn't introduce any new behavior into a regular language. Computed goto's/dispatching is critical for getting decent emulation speed in "microcoded" architectures (IBM, Alto, LispM, etc.). For example, in the Alto, one could logically "OR" data bits into the address register for the next microinstruction to achieve a multiway branch. Carl Hewitt (of "Actor" fame) might suggest that dispatching (with arguments) is all you wanted from an execute instruction in the first place. At 05:48 PM 3/15/2018, Tom Knight wrote:
The GE 645 also had an execute double instruction, which would execute pairs of instructions. I think there were severe constraints on the even/odd-ness of the source, and on the overlaps (none allowed) between segments. Truly a nightmare for hardware. Not sure it ever really worked.
On Mar 15, 2018, at 8:13 PM, Henry Baker <hbaker1@pipeline.com> wrote: Problems with XCT (execute one instruction):
* no clean/obvious semantics; semantics have to be worked out for each different instruction being "executed"
* only one level of execute (at least for IBM)
* originally used for *tables* of instructions, but what about variable-length instructions? (Similar problem to "skip" instructions)
* what are the semantics in the case of interrupts?
We now have architectures which support "virtual machines"; analogous problems at much larger scale.
At 04:47 PM 3/15/2018, rcs@xmission.com wrote:
PS: Does anyone else miss the XCT instruction? The 7094 & PDP6/10 had it, but it seems to have vanished. I guess it's an architectural nightmare for the hardware folks. --Rich
I implemented something similar in software --- an Atlas I machine-code emulator which output old and new addresses values of all registers accessed by each instruction as the target executed. AFAIK, it was used in earnest only once, in an attempt to locate a bug in a compiler which had defied all conventional attacks. The hapless programmer sat down with a pile of lineprinter output inches thick (the pile, that is --- to start with, anyway) and spent most of a day working through the test trace. Result: emulated test executed correctly, as specified! Implications of this discouraging experience being too gruesome to contemplate, the bug remained to lurk; the emulator was quietly retired in disgrace. WFL On 3/16/18, Henry Baker <hbaker1@pipeline.com> wrote:
Problems with XCT (execute one instruction):
* no clean/obvious semantics; semantics have to be worked out for each different instruction being "executed"
* only one level of execute (at least for IBM)
* originally used for *tables* of instructions, but what about variable-length instructions? (Similar problem to "skip" instructions)
* what are the semantics in the case of interrupts?
We now have architectures which support "virtual machines"; analogous problems at much larger scale.
At 04:47 PM 3/15/2018, rcs@xmission.com wrote:
PS: Does anyone else miss the XCT instruction? The 7094 & PDP6/10 had it, but it seems to have vanished. I guess it's an architectural nightmare for the hardware folks. --Rich
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On 15 Mar 2018 at 17:13, Henry Baker wrote:
Problems with XCT (execute one instruction):
[...]
* only one level of execute (at least for IBM)
On the PDP-1 (I know, more comments from the stone age) it did "infinite" levels of indirect, But: [...]
* what are the semantics in the case of interrupts?
The semantics were clear: indirect chains could be interrupted, and when the handler returned it'd start on the indirect again. If it made it to the end of the indirect chain, that instruction would execute and then the interrupt would happen. /Bernie\ Bernie Cosell bernie@fantasyfarm.com -- Too many people; too few sheep --
If I recall correctly, the PDP-10 had a similar situation with indirect memory references. Pointers had an "indirect" bit, and if set, the indirection would continue for as long as the pointer chain had the indirect bit set. Does anyone recall the details of how this worked? I assume the sequence could be interrupted and later resumed? Tom Bernie Cosell writes:
On 15 Mar 2018 at 17:13, Henry Baker wrote:
... On the PDP-1 (I know, more comments from the stone age) it did "infinite" levels of indirect, But: ...
It can be interrupted, but restarts from the beginning. A sufficiently long indirect chain will never finish with interrupts happening.
On Mar 15, 2018, at 9:33 PM, Tom Karzes <karzes@sonic.net> wrote:
If I recall correctly, the PDP-10 had a similar situation with indirect memory references. Pointers had an "indirect" bit, and if set, the indirection would continue for as long as the pointer chain had the indirect bit set.
Does anyone recall the details of how this worked? I assume the sequence could be interrupted and later resumed?
Tom
Bernie Cosell writes:
On 15 Mar 2018 at 17:13, Henry Baker wrote:
... On the PDP-1 (I know, more comments from the stone age) it did "infinite" levels of indirect, But: ...
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The PDP6 multi-level indirect addressing allowed one instruction to address a multi-dimensional array, with the coordinates taken from the accumulators (fast registers). The programmer created, for each dimension, a set of pointers into an array of the next higher dimension. These intermediate arrays are Margin Arrays. If the array indices are in accumulators A,B,C,D, and the array size is I*J*K*L, the fetch instruction would look like MOVE X,@MARA(A) @ means indirect address The margin arrays are MARA: @MARB(B); @MARB+J(B); @MARB+2*J(B); ... ; @MARB+(I-1)*J(B) MARB: @MARC(C); @MARC+K(C); ... ; @MARC+(I*J-1)*K(C) MARC: ARR(D); ARR+L(D); ... ; ARR+(I*J*K-1)*L(D) ARR: BLOCK(I*J*K*L) <--- the array data goes here Of course people came up with hacks. I wrote a program to tabulate 5x5 magic squares, and used the fancy addressing to calculate sums of partial rows in the partially filled-in magic square, in a single instruction. I calculated the expression 65-(A+B+C) in one instruction, with the intermediate margin arrays pointing to overlapping areas in one-dimensional arrays. Rich ------- Quoting Tom Karzes <karzes@sonic.net>:
If I recall correctly, the PDP-10 had a similar situation with indirect memory references. Pointers had an "indirect" bit, and if set, the indirection would continue for as long as the pointer chain had the indirect bit set.
Does anyone recall the details of how this worked? I assume the sequence could be interrupted and later resumed?
Tom
Bernie Cosell writes:
On 15 Mar 2018 at 17:13, Henry Baker wrote:
... On the PDP-1 (I know, more comments from the stone age) it did "infinite" levels of indirect, But: ...
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Well that makes a lot of sense! I always thought the arbitrarily deep levels of indirection were cool, but I wasn't sure how people actually used them in practice. I think BLISS-10 provided some level of support for the various PDP-10 addressing modes as well (which were dropped for DEC's releases of BLISS-16, BLISS-32, and I think even BLISS-36). The PDP-6/PDP-10 architectures really were ahead of their time in a lot of ways. I thought it was cool the way the accumulators could also be treated as memory locations. I even heard a claim that one of the Lisp garbage collectors was coded to run in the accumulators for efficiency. It seems to me that the main barriers to sticking with that architecture were the 36-bit word size, and the lack of byte addressability (not counting the very general "byte pointer" instructions). And of course DEC eventually abandoned the 36-bit processor line in favor of the VAX architecture. Tom rcs@xmission.com writes:
The PDP6 multi-level indirect addressing allowed one instruction to address a multi-dimensional array, with the coordinates taken from the accumulators (fast registers). The programmer created, for each dimension, a set of pointers into an array of the next higher dimension. These intermediate arrays are Margin Arrays. If the array indices are in accumulators A,B,C,D, and the array size is I*J*K*L, the fetch instruction would look like
MOVE X,@MARA(A) @ means indirect address
The margin arrays are
MARA: @MARB(B); @MARB+J(B); @MARB+2*J(B); ... ; @MARB+(I-1)*J(B)
MARB: @MARC(C); @MARC+K(C); ... ; @MARC+(I*J-1)*K(C)
MARC: ARR(D); ARR+L(D); ... ; ARR+(I*J*K-1)*L(D)
ARR: BLOCK(I*J*K*L) <--- the array data goes here
Of course people came up with hacks. I wrote a program to tabulate 5x5 magic squares, and used the fancy addressing to calculate sums of partial rows in the partially filled-in magic square, in a single instruction. I calculated the expression 65-(A+B+C) in one instruction, with the intermediate margin arrays pointing to overlapping areas in one-dimensional arrays.
Rich
------- Quoting Tom Karzes <karzes@sonic.net>:
If I recall correctly, the PDP-10 had a similar situation with indirect memory references. Pointers had an "indirect" bit, and if set, the indirection would continue for as long as the pointer chain had the indirect bit set.
Does anyone recall the details of how this worked? I assume the sequence could be interrupted and later resumed?
Tom
Bernie Cosell writes:
On 15 Mar 2018 at 17:13, Henry Baker wrote:
... On the PDP-1 (I know, more comments from the stone age) it did "infinite" levels of indirect, But: ...
Thank you all for making me feel young (something that happens less and less often). Jim Propp On Friday, March 16, 2018, Tom Karzes <karzes@sonic.net> wrote:
Well that makes a lot of sense! I always thought the arbitrarily deep levels of indirection were cool, but I wasn't sure how people actually used them in practice. I think BLISS-10 provided some level of support for the various PDP-10 addressing modes as well (which were dropped for DEC's releases of BLISS-16, BLISS-32, and I think even BLISS-36).
The PDP-6/PDP-10 architectures really were ahead of their time in a lot of ways. I thought it was cool the way the accumulators could also be treated as memory locations. I even heard a claim that one of the Lisp garbage collectors was coded to run in the accumulators for efficiency.
It seems to me that the main barriers to sticking with that architecture were the 36-bit word size, and the lack of byte addressability (not counting the very general "byte pointer" instructions). And of course DEC eventually abandoned the 36-bit processor line in favor of the VAX architecture.
Tom
rcs@xmission.com writes:
The PDP6 multi-level indirect addressing allowed one instruction to address a multi-dimensional array, with the coordinates taken from the accumulators (fast registers). The programmer created, for each dimension, a set of pointers into an array of the next higher dimension. These intermediate arrays are Margin Arrays. If the array indices are in accumulators A,B,C,D, and the array size is I*J*K*L, the fetch instruction would look like
MOVE X,@MARA(A) @ means indirect address
The margin arrays are
MARA: @MARB(B); @MARB+J(B); @MARB+2*J(B); ... ; @MARB+(I-1)*J(B)
MARB: @MARC(C); @MARC+K(C); ... ; @MARC+(I*J-1)*K(C)
MARC: ARR(D); ARR+L(D); ... ; ARR+(I*J*K-1)*L(D)
ARR: BLOCK(I*J*K*L) <--- the array data goes here
Of course people came up with hacks. I wrote a program to tabulate 5x5 magic squares, and used the fancy addressing to calculate sums of partial rows in the partially filled-in magic square, in a single instruction. I calculated the expression 65-(A+B+C) in one instruction, with the intermediate margin arrays pointing to overlapping areas in one-dimensional arrays.
Rich
------- Quoting Tom Karzes <karzes@sonic.net>:
If I recall correctly, the PDP-10 had a similar situation with indirect memory references. Pointers had an "indirect" bit, and if set, the indirection would continue for as long as the pointer chain had the indirect bit set.
Does anyone recall the details of how this worked? I assume the sequence could be interrupted and later resumed?
Tom
Bernie Cosell writes:
On 15 Mar 2018 at 17:13, Henry Baker wrote:
... On the PDP-1 (I know, more comments from the stone age) it did "infinite" levels of indirect, But: ...
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